1. Field of the invention
The invention relates to processes for forming metallization in insulating layers, and more particularly to forming metal features surrounded by an adhering diffusion barrier in an insulating layer of an electronic component using a maskless process.
2. Description of Related Art
In the evolution of integrated circuit chips, scaling down feature sizes improves performance of internal devices in the chips by increasing the speed and functional capability of the devices. As the devices get smaller, however, their performance becomes more heavily dependent on the interconnections between them. Likewise, as the number of devices per chip increases, the area required to route the interconnect lines exceeds the area occupied by the devices. This normally leads to integrated circuit chips with multilevel interconnect schemes.
In advanced microelectronic packaging of integrated circuits, particularly high-speed, high-density packaging for main frame computer applications, the chips are often mounted on multi-chip modules such as copper/polyimide substrates which contain buried wiring patterns to conduct electrical signals between various chips. These modules usually contain multiple layers of interconnect metallizations separated by alternating layers of an isolating dielectric whose function is to serve as electrical isolation between the metal features.
Any conductor material to be used in a multilevel interconnect has to satisfy certain essential requirements such as low resistivity, resistance to electromigration, adhesion to the underlying substrate material, stability (both electrical and mechanical) as ease of processing. Copper is often preferred due to its low resistivity, high electromigration resistance and stress voiding resistance.
Copper unfortunately suffers from high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide. This causes severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. The corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. A copper diffusion barrier is therefore often required.
The copper must also be patterned. Photolithography is a common approach wherein patterned layers are usually formed by spinning on a layer of photoresist, projecting light through a photomask with the desired pattern onto the photoresist to expose the photoresist to the pattern, developing the photoresist, washing off the undeveloped photoresist, and plasma etching to clean out the areas where the photoresist has been washed away. The exposed resist may be rendered insoluble (positive-working) and form the pattern, or insoluble (negative-working) and be washed away. In either case, the remaining resist on the surface forms the desired pattern. Photoresist, however, not only consumes time and resources but also endangers contamination from particulates and etchant solutions.
Dry etches may also be employed in copper patterning processes employing masks. However, dry etches tend to be resisted by copper. In addition, dry etches are expensive due to the high capitol cost of reaction ion etch (RIE) systems and are limited in application because they require a hard mask such as nickel, aluminum or gold.
Thus, a method of patterning copper without photolithography or dry etching is desirable.
Regardless of the conductor material or patterning technique, planarization of the interlayer dielectric is crucial for obtaining a multilevel structure that allows accurate lithographic patterning. The deposition and etchback tolerances associated with large film thicknesses are cummulative, and any non-planarity of the resist is replicated in the final top surface of the device. Chemical-mechanical polishing is a fast and efficient approach for achieving planarity in multichip modules and integrated circuits.